Conventional memory bit cells typically face a trade-off between stability and performance when implementing transfer gates to connect storage devices to bit lines. A higher Beta (β) ratio between the transfer gate and the storage device typically results in higher stability, whereas a lower Beta ratio typically results in improved writeability. Likewise, a higher Alpha (α) ratio between the transfer gate and the storage device typically results in higher stability, whereas a lower Alpha ratio typically results in improved writeability. This issue is further compounded in memory systems utilizing multiple power states.